ATMEL AT89C51 -> STC89C52RC-40I-PDIP

• Drain mode: < 0.1uA, wake up by external interrupt
• Idle mode: 2mA
• Normal mode: 4mA-7mA

Flash

8k bytes

RAM

512 bytes

I

-40C~+85C

12 clocks = 1 machine cycle

AMTEL AT89C52 PORT Pin

• P0.0~P0.7 Port0 :Port0 is an 8-bit bi-directional I/O port with pull-up resistance. Except being as GPIO, Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory.
• P1.0 ~ P1.7 Port1 : General-purposed I/O with weak pull-up resistance inside. When 1s are written into Port1, the strong output driving CMOS only turn-on two period and then the weak pull-up resistance keep the port high. P1.0 is also used as one of event sources for timer2, or output carrier of timer 2, alias T2. P1.1 is also used as one of interrupt-controlling sources for time 2, alias T2EX.
• P2.0 ~ P2.7 Port2 : Port2 is an 8-bit bi-directional I/O port with pull-up resistance. Except being as GPIO, Port2 emits the high-order address byte during accessing to external program and data memory.
• P3.0 ~ P3.7 Port3 : General-purposed I/O with weak pull-up resistance inside. When 1s are written into Port1, the strong output driving CMOS only turn-on two period and then the weak pull-up resistance keep the port high. Port3 also serves the functions of various special features. P3.0 and P3.1 act as receiver and transceiver of the data for UART function block, Alias RxD and TxD. P3.2 and P3.3 also act as external interrupt sources, alias /INT0 and /INT1. P3.4 and P3.5 also act as event sources for timer0 and timer1 individually, alias T0 and T1. P3.6 also acts as write signal while access to external memory,alias /WR. P3.7 also acts as read signal while access to external memory, alias /RD.
• RST Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. This pin drives High for 96 oscillator periods after the Watchdog times out. The DISRTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default state of bit DISRTO, the RESET HIGH out feature is enabled.
• ALE/PROG Address Latch Enable (ALE) is an output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external data memory.
• PSEN Program Store Enable (PSEN) is the read strobe to external program memory. When the AT89S52 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.
• EA/VPP External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming.
• XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
• XTAL2 Output from the inverting oscillator amplifier.

I/O Port programming

All port pin on STC89xx series may be independently configured to one of four modes: quasi-bidirectional(standard 8051 port output), push-pull output, input-only or open-drain output

• All the ports upon REST are configured as input, ready to be used as input ports
• When the first 0 is written to a port, it becomes an output
• To reconfigure it as an input, a 1 must be sent to the port
• P0 is an open drain, unlike P1, P2, and P3
• Port 3 has the additional function of providing some extremely important signals

Block diagram

Onboard Peripheral Schemas

I/O Port

P0.0~P0.7, P1.0~P1.7, P2.0~P2.7, P3.0~P3.7 All port pins on STC89xx series may be independently configured to one of four modes : quasi-bidirectional (standard 8051 port output), push-pull output, input-only or open-drain output. All port pins default to quasi-bidirectional after reset. Each one has a Schmitt-triggered input for improved input noise rejection.

Special Function Registers

A map of the on-chip memory area called the Special Function Register (SFR)

• Accumulator ACC is the Accumulator register. The mnemonics for accumulator-specific instructions, however, refer to the accumulator simply as A
• B Register The B register is used during multiply and divide operations. For other instructions it can be treated as another scratch pad register.
• PSW The program status word contains several status bits that reflect the current state of the CPU. The PSW, shown below, resides in the SFR space. It contains the Carry bit, the Auxiliary Carry(for BCD operation), the two register bank select bits, the Overflow flag, a Parity bit and two user-definable status flags. The Carry bit, other than serving the function of a Carry bit in arithmetic operations, also serves as the “Accumulator” for a number of Boolean operations. The bits RS0 and RS1 are used to select one of the four register banks shown in the previous page. A number of instructions refer to these RAM locations as R0 through R7. The Parity bit reflects the number of 1s in the Accumulator. P=1 if the Accumulator contains an odd number of 1s and otherwise P=0.
• Stack Pointer The Stack Pointer register is 8 bits wide. It is incremented before data is stored during PUSH and CALL executions. While the stack may reside anywhere in on-chip RAM, the Stack Pointer is initialized to 07H after a reset. This causes the stack to begin at location 08H
• Data Pointer The Data Pointer (DPTR) consists of a high byte (DPH) and a low byte (DPL). Its intended function is to hold a 16-bit address. It may be manipulated as a 16-bit register or as two independent 8-bit registers. For fast data movement, STC89xx series support two data pointers. They share the same SFR address and are switched by the register bit – DPS/AUXR1.0.

• Ports 0 to 3 P0, P1, P2 and P3 are the SFR latches of Ports 0, 1, 2 and 3, respectively.

• TMOD

• SCON

Addressing Modes

The CPU can access data in various ways, which are called addressing modes, Addressing modes are an integral part of each computer's instruction set. They allow specifying the source or destingation of data in different ways, depending on the programming situation. There eight modes available:

• Register
• Direct
• Indirect
• Immediate
• Relative
• Absolute
• Long
• Indexed

Memory Space

Program (CODE) memory

• Program (CODE) memory is read only; it cannot be written to.
• Program memory may be accessed from your C programs using the code memory type specifier.
• The 8051 executes programs stored in program memory only.
• 8K 00H ~ 1FH Internal memory
  • AP Application Program region AP region is the space that user program is resided
  • IAP In Application Program region IAP region is the nonvolatile data storage space that may be used to save important parameters by AP program
  • ISP In System Program (boot) region Inside the ISP region, the user can also enable read/write access to a small memory space to store parameters for specific purposes. Generally, the purpose of ISP program is to fulfill AP program upgrade without the need to remove the device from system.

Data memory

• has total of 128k bytes of memory space
• 64k bytes of code and 64k bytes of data, the code space are accessed using instruction MOVC A, @A+DPTR, while the data memeory space is accessed using the DPTR register and an instruction called MOVX, where X stands for external
• the data space cannot be shared between code and data
• in many applications we use RAM locations 30H-7FH as scratch pad
• we use R0~R7 of bank 0, leaves addresses 08H-1FH for stack usuage
• if we need more registers, we simply use RAM locations 30H-7FH
• it is registers, RAM, and I/O ports that need to be bit-addressable
• ROM, holding program code for execution, is not bit-addressable
• 120K 20H ~ 7FH Internal SRAM, 00H~7FH are Low 128K Interal RAM
• 128K 80H ~ FFH are High 128k Internal RAM (SFRs)

On-chip Scratch-Pad RAM

Auxiliary RAM

External RAM

Memory Type

Memory model

Data types

Power-on Reset

Upon applying a high pulse to REST(Pin 9), the microcontroller will reset and terminate all activites, this is often referred to as a power-on reset

• In order for the RESET input to be effective, it must have a minimum duration of 2 machine cycles.
• All the ports upon RESET are configured as output, ready to be used as input ports
• Port 0 is also designated as AD0-AD7, allowing it to be used for both address and data
• when connecting an 8051/31 to an external memory, port 0 provides both address and data
• ALE indicates if P0 has address or data, when ALE=0, it provides data D0-D7; when ALE=1, it has address A0-A7

Interrupt

ATMEL 80C51 CPU Timing

A machine cycle consists of 6 states (12 oscillator periods). Each state is divided into a Phase 1 half, during which the Phase 1 clock is active, and a Phase 2 half, during which the Phase 2 clock is active. Thus, a machine cycle consists of 12 oscillator periods, numbered S1P1 (State 1, Phase 1), through S6P2 (State 6, Phase 2). Each phase lasts for one oscillator period. Each state lasts for two oscillator periods. Typically, arithmetic and logical operations take place during Phase 1 and internal register-to-register transfers take place during Phase 2. The diagrams above show the fetch/execute timing referenced to the internal states and phases. Since these internal clock signals are not user accessible, the XTAL2 oscillator signal and the ALE (Address Latch Enable) signal are shown for external reference. ALE is normally activated twice during each machine cycle: once during S1P2 and S2P1, and again during S4P2 and S5P1. Execution of one-cycle instruction begins at S1P2, when the opcode is latched into the Instruction Register. If it is a two-byte instruction, the second byte is read during S4 of the same machine cycle. If it is one-byte instruction, there is still a fetch at S4, but the byte read (which would be the next opcode), is ignored, and the Program Counter is not incremented. In any case, execution is complete at the end of S6P2. Figure A and Figure B show the timing for a 1-byte, 1-cycle instruction and for a 2-byte, 1-cycle instruction. Most 80C51 instructions execute in one cycle. MUL (multiply) and DIV (divide) are the only instructions that take more than two cycles to complete. They take four cycles. Separately, two codes bytes are fetched from Program Memory during every machine cycle. The only exception to this is when a MOVX instruction is executed. MOVX is a 1- byte 2-cycle instruction that accesses external Data Memory. During a MOVX, two fetches are skipped while the external Data Memory is being addressed and strobed. Figure C and Figure D show the timing for a normal 1-byte, 2-cycle instruction and for a MOVX instruction.

Development

• Code Editor(windows) - Keil uVision5
• Compiler - Uploader STC-ISP

Checking target MCU ...
  MCU type: STC89C52RC/LE52RC
  F/W version: 6.6.4C

Current H/W Option:
  . Current clock frequency: 11.030MHz
  . System use 12T mode
  . Oscillator gain is HIGH
  . Any reset source can stop WatchDog if WatchDog timer is running
  . Internal XRAM is ENABLE
  . ALE pin behaves as ALE function pin
  . Do not detect the level of P1.0 and P1.1 next download
  . Do not erase user EEPROM area at next download

  MCU type: STC89C52RC/LE52RC
  F/W version: 6.6.4C


Re-handshaking ... Successful           [0.594"]
Current Baudrate: 115200
Erasing MCU flash ...  OK !     [0.313"]
Programming user code ... OK !      [0.734"]


  Complete !(2023-01-21 10:51:43)

Header file

• stdio.h
• intrins.h
• math.h
• reg51.h
• reg52.h
• AT89X52.H

Sample codes

• Power Mangement

Expirements

• LED
• Beep
• Button
• Interrupt
• Timer/Counter
• Serial
• LCD_1602A
• Infrared Transmit & Receiver
• Audio
• Matrix Keyboard
• Step Motor
• Ultra-sonic

1. include
2. sample
3. sensors
4. io
5. peripherals
6. scon
7. tmod